This invention relates to microprocessors, and more particularly, to microinstruction and operand addressing in microprocessors.
Prior microprocessors have typically included a control store which provides a class of microinstructions to address the control store itself, and a second class of microinstructions to address the main computer memory to read and write operands in memory.
It has also been typical to provide a variety of alternate addressing sources for the control store ROM. For example, such sources have included registers connected to the main data bus and loaded by the arithmetic logic unit; incrementing logic for addressing successive microinstructions; and address register stacks used to store return addresses when nested looping operations were undertaken.
Typically, the second class of microinstructions in the microinstruction register, supplied by the control store, which provides the next operand address, has imposed significant delays on system operation. Since operands, especially substantial arrays of operands which could not be stored in simple register structures, have typically been addressed in the main memory of the system, using multiple address commands from the control store, the cycle time for manipulating such data has been relatively long. This has posed significant problems when the microprocessor is used for real time applications requiring extremely high through-put of data.
In such applications, the time required in the prior art was further increased by the fact that the operand was typically addressed by a first microinstruction, and a second microinstruction defining the manipulation of that operand was typically addressed in a successive microcycle, so that plural microinstruction steps were required to address and manipulate the data, effectively wasting microcycles during the fetching and storing of the operands.
While indirect addressing techniques are known in the prior art, such as, for example, techniques which allow offsetting of a microinstruction address provided by the microinstruction register, the prior art has not provided flexible addressing which will permit an address provided by the arithmetic logic unit to be offset by a base, also provided by the arithmetic logic unit, to permit loop strings of microinstructions to be implemented or two-dimensional arrays of operand data to be addressed.